Příklady

And-Or-Invert včetně definovaného zpoždění

library IEEE;
use IEEE.STD.LOGIC_1164.all;

entity AOI is
port
(
    A, B, C, D : in STD_LOGIC;
    F          : out STD_LOGIC;
);
end AOI;

architecture V2 of AOI is
    signal AB, CD, O : STD_LOGIC;
begin
    AB <= A and B after 2 NS;
    CD <= C and D after 2 NS;
    O <= AB or CD after 2 NS;
    F <= not 0 after 1 NS;
end V2;

Použití AOI v jiném funkčním bloku

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity MUX is
port
(
    SEL, A, B : in STD_LOGIC;
    F         : out STD_LOGIC
);

end MUX;

architecture STRUCTURE of MUX is

component INV
port
(
    A : in STD_LOGIC;
    F : out STD_LOGIC
);
end component;

component AOI
port
(
    A, B, C, D : in STD_LOGIC;
    F          : out STD_LOGIC
);

end component;

signal SELB: STD_LOGIC;

begin
    G1: INV port map (SEL, SELB);
    G2: AOI port map (SEL, A, SELB, B, F);
end;

Invertor

library IEEE;
use IEEE.STD.LOGIC_1164.all;

entity inv is
generic ( td : time := 1 ns );
port
(
    a : in std_logic;
    y : out std_logic;
);
end inv;

architecture behave of inv is
begin
    y <= not a after td;
end behave;

Dvouvstupové hradlo NAND

library IEEE;
use IEEE.STD.LOGIC_1164.all;

entity nand2 is
generic ( td : time := 1 ns );
port
(
    a, b : in std_logic;
    y    : out std_logic;
);
end nand2;

architecture behave of inv is
begin
    y <= a nand b after td;
end behave;

Přenosové hradlo CMOS

library ieee;
use ieee.std_logic_1164.all;

entity switch is

generic ( td : time := 1 ns );
port
(
    c, cn : in std_logic; 
    a     : in std_logic;
    y     : out std_logic
);
end switch;

architecture behave of switch is
begin
    process( c, cn, a )
        begin
        if (c = '1') and (a = '0') then
            y <= '0' after td;
        else
            if (cn = '0') and (a = '1') then
                y <= '1' after td;
            else
                if ((c = '0') or (a = '1')) 
                    and ((cn = '1') or (a = '0')) then
                    y <= 'Z' after td;
                end if;
            end if;
        end if;
    end process;
end behave;