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Altera Announces MAX Roadmap with 3.3-V, ISP-Capable Michelangelo Family

Altera recently unveiled plans for the next-generation MAX programmable logic device (PLD) family, code-named Michelangelo. Expected to begin shipping in 1998, Michelangelo devices will range from 32 to 1,008 macrocells, will operate at 3.3-V, and will offer in-system programmability (ISP).

Altera plans to manufacture Michelangelo devices on a 0.35-micron, quad-layer metal EEPROM process. These devices will operate at a 3.3-V core voltage level, and with Altera's MultiVolt interface, Michelangelo devices will be able to interface with 5-V, 3.3-V, or 2.5-V devices. The advanced process and 3.3-V core voltage can improve performance and reduce power consumption by 40%.

Vertical pin migration and architectural similarities will make it easy for MAX 7000 and MAX 9000 designers to implement designs in Michelangelo devices. Altera plans to make 32-, 64-, 128-, and 256-macrocell Michelangelo devices pin-compatible with the popular 5-V MAX 7000S family, allowing you to begin designing with 5-V MAX 7000S device and later migrate to 3.3-V Michelangelo devices.

Planned features include:

  • High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on fourth-generation Multiple Array MatriX (MAX¨) architecture
  • 3.3-V in-system programmability (ISP) through the built-in Joint Test Action Group (JTAG) interface with advanced pin-locking capability
  • Manufactured on a 0.35µm, four-layer metal process
  • Pin-compatible with the popular 5.0-V MAX 7000S family
  • High-density EPLD family ranging from 600 to 20,000 usable gates
  • 5-ns pin-to-pin logic delays with counter frequencies to 178.6 MHz
  • MultiVolt I/O interface enabling device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
  • Pin counts ranging from 44 to 356 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), and plastic J-lead chip carrier (PLCC) packages
  • ClockBoost option for clock multiplication
  • FastTrack Interconnect continuous routing structure for fast, predictable performance
  • PCI compliant
  • Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
  • Software design support and automatic place-and-route provided by Altera's MAX+PLUS II development system on 486- and Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000 workstations

ISP Provides Flexibility

All members of the Michelangelo family will be 3.3-V ISP-capable and provide superior pin-locking capability. You will be able to program Michelangelo devices with automatic test equipment (ATE), embedded processors, or Altera programming hardware. ISP enables in-field upgrades, reducing the need for expensive equipment reworking (see the figure below).

Mount Unprogrammed Program In-System Reprogram in the Field
  • Eliminates damage from device handling
  • Prevents bent leads
  • Easy prototyping
  • Allows generic end-product inventory
  • Specific test protocol or algorithm can be programmed during manufacturing or test flow
  • No need to return system for upgrades
  • Add enhancements quickly & easily

MultiVolt Interface

Altera's MultiVolt interface will allow you to seamlessly incorporate Michelangelo devices with devices of varying voltage levels. Today's printed circuit boards are often a mix of conventional 5-V devices and 3.3-V devices. The central interface device--often a high-density PLD--must be able to connect with these different devices. MultiVolt-enhanced Michelangelo devices will run on 3.3-V, and will have I/O pins that are compatible with 5-V, 3.3-V, or 2.5-V logic levels.

Michelangelo Family Members

Altera expects the Michelangelo family to contain from 32 to 1,008 macrocells in a variety of packages, including plastic J-lead chip carrier (PLCC), quad flat pack (QFP), and ball-grid array (BGA) packages (see Tables 1 and 2). Michelangelo devices will be supported by Altera's industry leading MAX+PLUS II development system. Currently in the design phase, the first Michelangelo devices are planned for the first half of 1998.

Table 1. Michelangelo Device Features
FeatureM32M64M128M256
Usable gates 600 1,250 2,500 5,000
Macrocells 32 64 128 256
tPD (ns) 5 5 5 6
Packages 44-pin PLCC
44-pin TQFP
44-pin PLCC
44-pin TQFP
84-pin PLCC
84-pin PLCC
100-pin TQFP
144-pin TQFP
144-pin TQFP
208-pin PQFP
256-pin BGA

Table 2. Michelangelo Device Features
FeatureM400M560M768M1008
Usable gates 8,000 12,000 16,000 20,000
Macrocells 400 560 768 1,008
tPD (ns) 7.5 7.5 9.0 9.0
Packages 144-pin TQFP
208-pin PQFP
256-pin BGA
144-pin TQFP
208-pin PQFP
256-pin BGA
144-pin TQFP
208-pin PQFP
256-pin BGA
356-pin BGA
208-pin PQFP
256-pin BGA
356-pin BGA



Last Updated: 4/25/97 webmaster@altera.com.
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