PLD Glossary
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Architecture: The common logic structure of a family of programmable integrated circuits.

ASIC (Application Specific Integrated Circuit): IC product customized for a single application.

ATE (Automatic Test Equipment): Equipment that automatically tests populated circuit boards and can be used to program Lattice ISP devices.

Boolean Equation: Text-based design entry method based upon boolean algebra.

Boundary Scan Test: Emerging trend in board-level testing. Provides lower test and manufacturing costs primarily for high pin count devices due to the silicon overhead required to implement the technology.

Cell-Based PLD: Hybrid PLD architecture combining standard CPLD logic with specialty function blocks on the same chip.

CMOS (Complementary Metal Oxide Semiconductor): Advanced IC manufacturing process technology characterized by high integration, low cost, low power and high performance. CMOS is the preferred process for today's high density PLDs.

CPLD (Complex Programmable Logic Device): High density PLD containing macrocells that are interconnected through a central Global Routing Pool. This type of architecture provides high speed and predictable performance. Generally the preferred architecture for implementing high speed logic. Preferred programmable technology is E2CMOS(r).

Density: Relative measure of the amount of logic, measured in gates, that may be integrated into a single IC. Higher density equates to more gates. Often used interchangeably with complexity.

Design Simulation: Process of ascertaining whether a design performs the specified functional and timing behavior.

EDA (Electronic Design Automation): Generic name for software that assists in the design of electronic circuits.

E2CMOS(r) (Electrically Erasable CMOS): Lattice's proprietary process, considered the preferred process technology for PLDs due to its inherent performance, reprogrammability and testability benefits.

Fmax: Symbol for maximum frequency, which is the maximum number of times per second that a chip can generate logic functions.

FAE (Field Application Engineer): Engineer who provides on-site technical support for customer applications.

Fabless: Class of semiconductor companies that design, market and sell ICs, but subcontract wafer manufacturing by forming alliances with silicon wafer manufacturers.

Fitter: Software used for optimizing and partitioning a logic design before placing and routing the design into a targeted programmable device.

Foundry: Silicon wafer fabrication facility. Also called a fab.

FPGA (Field Programmable Gate Array): High density PLD containing small logic cells interconnected through a distributed array of programmable switches. This type of architecture produces statistically varying results in performance and functional capacity, but offers high register counts. Programmability typically is via volatile SRAM or one-time-programmable antifuses.

GAL(r) (Generic Array Logic): Family of low density devices invented by Lattice Semiconductor.

Gate: The most basic logic element. More gates equates to higher density.

Gate Array: IC that is customized by interconnecting an array of logic elements. Customization is performed by the manufacturer and typically involves non-recurring engineering (NRE) costs and several design iterations.

GLB (Generic Logic Block): Standard logic block of Lattice Semiconductor's high density ispLSI(r) and pLSI(r) devices. Each GLB contains inputs and outputs along with the logic required to implement most logic functions.

GRP (Global Routing Pool): Proprietary interconnect structure that enables the output from the GLBs or the I/O cell inputs to be connected to the inputs of the GLBs. Lattice GRPs provide fast, predictable speeds with complete connectivity.

High Density PLD: PLD with more than 1000 gates.

I/O Cell (Input/Output Cell): Logic cells which receive input signals from the device pins and/or provide output signals.

ISP(tm) (In-System Programmability(tm)): Pioneered by Lattice, Lattice ISP products can be programmed and reprogrammed right on the system board. ISP products are revolutionizing the world of programmable logic by dramatically reducing time-to-market and production costs, and providing a cost effective means to upgrade systems installed in the field.

ispATE(tm): Comprehensive software package enabling the use of automated test equipment to: 1) utilize Lattice ISP devices to perform board tests and 2) program ISP devices.

ispCODE(tm): Lattice Semiconductor proprietary software consisting of C source code algorithms for performing all the functions required to control the programming of Lattice ISP devices. The code can be integrated into a customer's system, allowing ISP devices to be programmed directly via an on-board microprocessor or microcontroller.

ispDaisy Chain Download Software: Lattice Semiconductor proprietary device download package that provides capability to program multiple devices simultaneously on a board.

ispDS+(tm): Lattice Semiconductor's third-party compatible HDL synthesis optimized logic fitter supporting PC and workstation platforms. ispDS+ combines third-party CAE tools for design entry and verification with Lattice's Fitter, offering a powerful and complete development solution. Third-party CAE environments include: Cadence, Data I/O - Synario, Exemplar Logic, ISDATA, Logical Devices, Mentor Graphics, OrCAD, Synopsys, Synplicity and Viewlogic.

ispGAL(r): GAL with in-system programmability features.

ispGDS(tm): Lattice Semiconductor's proprietary ISP switch matrix used for signal routing and DIP switch replacement.

ispLSI(r): Name for Lattice's performance leading family of CPLD products. World's first high density product line offering nonvolatile, in-system programmability. ispLSI parts provide unparalleled system performance.

ispSTREAM(tm): JEDEC files converted to a bit-packed format, which consumes 1/8 the storage space of the original file.

JEDEC file: Industry standard pattern information used to program ispLSI parts.

JTAG (Joint Test Action Group): Set of specifications that enables board and chip level functional verification of a board during production.

Logic: One of the three major classes of ICs: microprocessors, memory and logic. Logic is used for data manipulation and control functions.

Low Density PLD: PLD with less than 1000 gates. Also known as SPLD.

Macrocell: Group of logic cells that takes the basic sum-of-products logic and adds functionality through features like storage elements, path controls, polarity and feedback.

OLMC (Output Logic Macrocell): D-type flip-flop with an Exclusive-OR gate on the input, enabling each GLB output to be configured as either combinatorial or registered.

ORP (Output Routing Pool): The ORP routes signals from the GLB outputs to I/O cells configured as outputs or bi-directional pins. This structure provides greater flexibility for assigning and locking I/O pins and routing signals into and out of the device.

pDS(r): Lattice Semiconductor's proprietary Windows-based software development system. The comprehensive package provides a convenient, low cost and easy to use set of tools for device design and implementation.

Pin: Metal connection point attached to an IC package used to: 1) transmit electrical signals to and from the integrated circuit and 2) attach the IC to the circuit board.

PLD (Programmable Logic Device): Digital IC that can be programmed by the user to perform a wide variety of logical operations. SPLDs, CPLDs and FPGAs are classes of PLDs.

Process Technology: The manufacturing process used to transform blank silicon wafers into finished wafers containing hundreds of thousands of chips. Typically distinguished by technology type (e.g., E2CMOS) and line width geometry (e.g., 0.35 micron).

Programmer: Stand-alone electronic equipment used to program traditional PLDs via a socket. Programmers are not required with Lattice ISP devices.

Schematic Capture: Graphical method of design entry.

SPLD (Simple PLD): PLD with less than 1000 gates. Also known as Low Density PLD.

tpd: Symbol for propagation delay, the time it takes for an output signal to change as a result of a change in the input signal.

TQFP (Thin Quad Flat Pack): Type of IC packaging that significantly reduces the amount of space required by a chip on a circuit board. TQFP packaging is ideal for space conscious applications such as PCMCIA cards.

UltraMOS(r): Lattice Semiconductor's proprietary manufacturing process technology.

Verilog-HDL: A proprietary, high level, text-based design entry language.

VHDL: VHSIC hardware description language, a high level text-based design entry language.